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Protocol certification ensures that individual components on a chip-level bus can function correctly. System-level busses linking multiple components display an enormous number of possible configurations and it’s infeasible to adequately verify them using system-level simulation alone. This method is a divide-and-conquer approach to verify components individually yet exhaustively.
The general area of protocol certification encompasses:
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- Both master / slave configuration and verification: Formal property languages can capture protocol rules precisely in an executable format. Using the assume-guarantee approach of arranging the resulting properties, the same description can be applied to both masters and slaves of a specific protocol. Formal verification of both masters and slaves using the same set of protocol properties ensures the masters and slaves interact with one another properly under all legal operating conditions.
- Verifying standard protocols such as AHP, AXI, etc.: Formal property verification can capture protocol rules precisely in an executable format and confirm that a block of RTL obeys the protocol rules in all cases. For standard protocols, it is especially high on return-on-investment, since standard protocol properties which have been already applied to numerous RTL development projects may be commercially available.
- Verifying proprietary protocols that may be involved in the design: As with standard protocols, for proprietary protocols, formal verification is a great way to ensure correctness, document and maintain consistency among different projects, avoid the potential confusion and imprecision of a paper document. Project teams can rapidly learn a new protocol and compare changes between revisions.
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