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Formal Methodology Validates Cache-Coherence Protocol
Bugs in RTL code are problematic, but a bug in an architectural specification can be catastrophic. If the bug remains undetected until post-silicon debugging, the design process essentially starts all over again. |
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Real Men (and Women!) Use IP
Legendary AMD founder Jerry Sanders once remarked that “real men have fabs,” a notion that seemed perfectly reasonable at the time. Of course, that was before the rise of industry behemoths like TSMC. Foundries are now the manufacturing powerhouses, and modern fabless semiconductor companies can themselves quip, “Who needs fabs?”
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Design Trust and Verification
It's generally acknowledged that we have entered the 45 nm processing node era. It's also well known that at this node the mantra among SoC designers should be "verify!, verify!, verify!" |
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Dispelling Verification Myths Critical for 45-nm Designs
As designers approach 45 nm, the difference between ASICs and SoCs really blurs and, essentially, all chips become SoCs. At the same time, platform-based design, with the use and reuse of internal and external IP blocks, is playing a bigger and bigger role, because nobody is going to build a 50-M gate chip from scratch. |
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Jasper Introduces Multi-Proof JasperCore for Verification
JasperCore harnesses the proven capabilities of the company’s formal analysis engines to boost productivity and decrease the cost of deployment by performing numerous parallel runs using ProofGrid™, a new capability that distributes formal technology. |
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Mixing Formal and Dynamic Verification, Part 2
In this second part of our report, we discuss the detailed survey results, see how formal is being used with dynamic verification, look at the application of formal in the ESL space, and hear from technology users and technology providers how formal methods might look in 2012. Plus see our formal cartoon! |
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Women in Technology: Crashing the Silicon Ceiling
My own career in high-tech has been a wonderful adventure, a challenging voyage spanning technology, international business, and a network of extremely intelligent and driven colleagues. Electrical engineering, even more than most disciplines, has transformed our lives. I would definitely recommend a career in technology to any woman, or man…It is positive, enjoyable, and lucrative!
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DAC 2009
Thanks to those of you who visited Jasper at DAC 2009 in San Francisco! Highlights included demos of exciting new capabilities in JasperGold, JasperCore and ActiveDesign formal verification solutions, a Forum presentation on design develoment and reuse with ActiveDesign, Rajeev Ranjan on the Verification Debug panel, Kathryn Kranen moderating a DAC Pavilion panel, and Holly Stump on the WWINDA panel. If you could not attend, but are interested in demos of the latest Jasper solutions, please see the links to our new video demos in this newsletter! |
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User Group Meeting
November 2009
Jasper Design Automation will hold its annual Users Group Meeting in November, 2009. Please check the website for more information, and how to register. |
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IP'09 Conference
12/1/09 - 12/3/09
Grenoble, Franceip
Kathryn Kranen, Program Committee
Panel on IP and Design Leverage
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To meet with the design and verification deployment experts at Jasper at any of the above conferences,
please send email to info@jasper-da.com or call 1.650.966.0266.
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www.jasper-da.com
Jasper Design Automation, 100 View Street,
Suite 101, Mountain View, CA 94041, USA
Tel: +1 650 966 0200 Fax: +1 650 625 9840 |
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