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In The News

2010


March 12	cvcblr.com	Twitter of RTL design – welcome to Behavioral Indexing!
March	ocpip.org	OCP-IP Papers & Presentations
March 03	youtube.com	Jasper Design Automation at DVCon 2010: Kit Bridges
March 02	electronicdesign.com	Formal Analysis: A Valuable Tool for Post-Silicon Debug
March 02	cadence.com	DVCon Panel: Three Ways To Minimize Verification Effort
February 22	eetimes.com	Jasper releases LPDDR, DDR3 proof kits
February 19	marketwire.com	Jasper ActiveDesign EDN Innovation Award Finalist
February 18	finance.yahoo.com	EASii IC Working With Jasper to Promote Formal Innovations in Europe
February	EDSF	Japanese Design and Verification Teams Report High ROI with Jasper
February 16	elektronikpraxis.vogel.de	Lückenlose Prüfung komplexer Chip-Designs im Post-Silicon-Debugging durch Tools der formalen Verifikation
February 12	techbites.com	Formal is more than just alive and well. It is thriving!
February 11	scdsource.com	Using formal verification for SoC integration
February 09	eon.businesswire.com	Jasper Design at DVCon: Showcasing Latest Formal Verification Advances, Participating in Prestigious Panel
January 20	gabeoneda.com	May You Live in Interesting Times
January 18	Nikkei Tech-on! (Japanese)
January 18	EDA Express (Japanese)
January	EDSF (Japanese)
January 12	Yahoo Finance	Newest Jasper Formal Technology Coming to EDSF, January 28-29, Yokohama

2009


December 18	Elektronik i Norden (Sweden)	IP/ESC 09
December 15	EDN	EDN Hot 100 Electronic Products of 2009
December 15	SystemVerilog for Verification	Formal Verification – Model Checking case study from SUN & Jasper – excellent read
December 09	EE Times	Panelists look at IP quality versus design productivity
December 04	ELETTRONICA OGGI WEB (Italy)	IP/ESC’09: dall’IP ai sistemi embedded
November 17	Yahoo Finance	Jasper CEO Kathryn Kranen Speaking at IP-ESC 2009
November 05	Yahoo Finance	Lawrence Loh Promoted to Vice President of Worldwide Applications Engineering at Jasper Design Automation
November 04	EE Times	Top 10 women in microelectronics
October 27	Chip Design	Teens and Tech: What’s Hot and What’s Not!
October 27	HLDTV	Jasper Chief Architect Ziyad Hanna Presenting At IEEE High-Level Design Conference Nov. 6, San Francisco
October 21	ARM Techcon	Imagining New IP Architectures: Formal Verification Conquers the Void
October 19	Chip Design	Applying Formal Methods to a PCI-Express Transmit Retry Buffer
September 28	EDACafe	It’s the Customers
September 8	D&R Industry Articles	Survey of Chip Designers on the Value of Formal Verification Across the Spectrum of Applications
September 3	EDA DesignLine	Survey has designers assign ROI to verification chores
Aug 10	EDACafe	Jasper's EDACafe Video interview from DAC!
July 24	SCDSource	SCDsource’s ten hot technologies to see at DAC 2009
July 23	Electronic Design	Formal Methodology Validates Cache-Coherence Protocol
July 17	Tech On	JasperCore in Nikkei Electronics TechOn – (Japanese)
July 16	Chip Design	Women in Technology: Crashing the Silicon Ceiling
July 14	DACeZine	Real Men (And Women!) Use IP
July 13	EDA DesignLine	Jasper offers JasperCore verification methodology
July 13	Chip Design	Jasper Introduces Multi-Proof JasperCore for Verification
July 13	SCDSource	Jasper Introduces Multi-Proof JasperCore and ProofGrid
July 13	Verification Vertigo	Innovations in formal verification
July 13	EDN	Jasper introduces updates to its formal verification and design tools
July 13	EE TIMES	Dispelling verification myths critical for 45-nm designs
June 30	EDA DesignLine	Design trust and verification
June 25	Jasper DAC	A Formal Affair – Booth 3767
June 18	Chip Design	Formal Verification Deployment Reveals Return On Investment
May 29	SCDSource	Mixing Formal and Dynamic Verification, Part 2
May 26	IC Journal	Demonstrating Targeted ROI - Key to Meaningful EDA Business Partnerships
May 19	EDACafé	ARM Selects Jasper for Formal Verification of IP
May 10	EE Times	Jasper, AMD ink long-term formal verification deal
April	Flash Demos	Jasper Design Overview: Flash
April	Flash Demos	JasperGold Solutions: Flash
April	Flash Demos	ActiveDesign Solutions: Flash
April 30	SCDSource	Mixing Formal and Dynamic Verification
April 22	DeepChip	Jasper on John Cooley's DeepChip
April 6	EDA Confidential	Kathryn Kranen: Celebrating Natural Selection in EDA
March 16	EDN	EDN Guest blog: Kathryn Kranen
March 13	iec.org	Video Interview: CTO Rajeev Ranjan, DesignCon 2009
February 25	EE Times	Verification tools step up
February 3	DesignCon	Toward Harnessing the True Potential of IP Reuse
January 19	SCDSource	Formal technology fuels 'behavior-based' RTL analysis

2008


December 16	SCD Source	Formal verification enables safe X handling
September 3	SCD Source	Formal verification checks IC power reduction features
August 5	SoC Central	Combining Metrics from Simulation and Formal
June	iec.org	Video Interview, CEO Kathryn Kranen, DAC 2008
June 5	SCD Source	Ten top technology developments to see at DAC
May 20	SCD Source	Time to reconcile the design/verification divorce
May 14	SCD Source	Jasper boosts formal verification proof capacity
May 10	EE Times	Verifying Configurable Verification Interfaces Using OCP
April 23	SCD Source	Using formal verification for post-silicon debug
April 14	Electronic Design	Modeling Extensions Help Verify Datapath Designs
February 19	SCDSource	Formal property checking -- what the users say
February 2	Electronic Design	Formal Verification Takes To "Sandbox"

2007

December 14	EE Times	Accellera seeks verification coverage standard
July 19	EE Times	Latest Jasper release touts better user experience
July 10	EE Times	Formal verification: where to use it and why
February 08	EE Times	Panelist seek ROI in IC verification