Jasper Design Automation is a privately-held Electronic Design Automation (EDA) company leveraging formal technologies to deliver high value/high ROI solutions for the design and verification of electronic systems and semiconductors. The company's production-proven formal verification solutions have been used on over 100 successful chip projects. System architects, logic designers, verification engineers and silicon bring-up teams are able to successfully prove protocols and executable specs; to design, explore and debug RTL; to ensure correctness of block-level functionality; and for rapid silicon validation and debug. Jasper's newly announced design solution drives greater RTL design quality and designer productivity. It is the first EDA solution for behavior-based RTL analysis and verification by logic designers that also accelerates knowledge transfer, improves design maintenance, and enables efficient reuse. Jasper solutions provide high value to both novice and advanced users.

Jasper's JasperGold® Verification System delivers the industry's highest proof capacity, for seamless scalability from formal assertion-based verification (ABV) to exhaustive end-to-end proofs of micro-architecture-level properties. With its automated Formal Scoreboard™ and Proof Accelerators™, JasperGold can validate complex designs that include packet-based data transportation, FIFOs, memories, caches and multiple clock domains. JasperGold delivers superior formal verification performance enabled by powerful, patented advanced formal techniques and state-of-the-art core engines. JasperGold's context-sensitive proof visibility and interactive Design Tunneling™ empower users to prove the correctness of critical design functionality.

Jasper's ActiveDesign™ is powered by formal analysis and Jasper's new Behavioral Indexing™ technology. This new solution delivers dramatic breakthroughs in design comprehension, driving higher RTL design quality and greater designer productivity. Jasper's Behavioral Indexing technology enables ActiveDesign to iteratively extract, index and store relevant design behaviors, along with the RTL, in a dynamic, executable database referred to as the Activated Design™. Activated Designs are optimized for complex yet flexible behavior-based analysis and automatic regressions, and work seamlessly with Jasper's formal property verification system, JasperGold® .

Aimed primarily at logic designers, ActiveDesign is used to confirm and index intended functional behaviors as the RTL is composed, and to easily validate complex, sometimes unintended, interactions among behaviors. This use mode is sometimes referred to as a "Designer Self Test." The powerful comprehension features in ActiveDesign help designers and verification engineers that 'inherit' a design to become intimately familiar with relevant design functionality, without any access to the original design author. Activated Designs empower any user over the life of the design, or its derivatives, to comprehend, safely modify, and retarget the RTL design for new uses.

Funding