SoC Integration poses verification challenges that have steadily become more complex, as designs continue to grow. Today’s SoCs combine large IP blocks; high-speed IOs, complex low-power implementations, and custom debug and test logic. These are managed by chip-level controllers, often with software- configurable status registers to help customize and control their operation. The boundaries between the various blocks for the SoC, and their changing interaction and specification, are often the focus of verification and pose the most pressing challenges.
The Jasper SoC Integration solution includes
- Automated register verification to prove data integrity of register fields and reset values
- Glitch verification to identify and verify possible glitches in the design
- Multi-cycle path verification to accurately verify multi-cycle path waivers
- Chip-level connectivity to exhaustively prove that RTL matches connectivity definition
Learn more about the JasperGold Formal Property Verification App for addressing formal property verification issues.