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About Jasper

Jasper Design Automation's mission is to make full formal IC verification a competitive advantage for its customers. Jasper's formal verification solutions are used by logic designers, verification engineers and silicon bring-up teams to design, explore and debug RTL, to ensure correctness of block-level functionality and for rapid post-silicon validation and debug. JasperGold® Verification System delivers complete deep formal systematic verification, ensuring correctness of critical design features without any testbench development.

About News

01/20/2010 May You Live in Interesting Times
01/14/2010 Jasper Advanced Formal Solutions at EDSF – Adding Value Throughout Design Flow
01/12/2010 Jasper Newest Formal Technology Coming to EDSF Jan. 28-29, Yokohama
On-Demand Webinar - IP Reuse vs. IP Leverage: What's the difference, and what are the issues?
12/18/2009 IP/ESC 09
12/15/2009 Jasper Wins: EDN Hot 100 Electronic Products of 2009
12/09/2009 Panelists look at IP quality versus design productivity
11/17/2009 Jasper CEO Kathryn Kranen Speaking At IP-ESC 2009
11/05/2009 Lawrence Loh Promoted to Vice President of Worldwide Applications Engineering at Jasper Design Automation
11/04/2009 Top 10 women in microelectronics
10/27/2009 Teens and Tech: What’s Hot and What’s Not!
10/27/2009 Jasper Chief Architect Ziyad Hanna Presenting At IEEE High-Level Design Conference Nov. 6, San Francisco
10/21/2009 Imagining New IP Architectures: Formal Verification Conquers the Void
10/19/09 Applying Formal Methods to a PCI-Express Transmit Retry Buffer
Jasper Design Automation Formal Verification Survey
Jasper-Formal Verification News and Events
Spectrum of Architectural Verification   RTL Development   RTL Block Verification   Protocol Certification  Low-power Verification SoC Integration  Post-silicon Debug   Design and IP Leverage
 
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